For this project I developed a simple clock timer system to test my ability to do state logic as apposed to using integrated circuits like the NE555 Timer IC.
Design
The design for the timer was simple, I wanted to use basic logic gates to create a device that simply counts the states, the decimal system transfers the logic to the next 7 segment display when it reaches it's maximum
Conclusion
This design was simple yet interesting and surprisingly challenging enough to keep me interested. I also loved learning to use Virtual Circuit Board as it make the designs very visually appealing.